The present disclosure relates to random access memories (“RAMs”), and more particularly, to an apparatus and method for segmenting bit lines in RAMs.
In a typical computing system, a memory hierarchy supports a central processing unit (“CPU”) with data storage capabilities. Generally, the type of memory device used as the primary random access memory (“RAM”) in a computing system is dynamic random access memory (“DRAM”). DRAM is comparatively low in cost and high in density, facilitating the storage of large quantities of data within a small volume of the computing system. Unlike static random access memory (“SRAM”), which generally has a lower density than DRAM, data stored in DRAM must be refreshed periodically to prevent the data from being lost due to charge leakage from the DRAM memory cells.
Since data stored in DRAMs discharges after remaining idle for a period of time, DRAMs require refresh cycles to maintain their data. Memory cells in DRAMs must be periodically refreshed within a certain period of time. Each DRAM memory is typically organized into memory banks, with each memory bank having a corresponding sense amplifier (“SA”). Data refresh is typically accomplished by accessing each row in each memory bank, one row at a time. When the memory banks are accessed to be refreshed, data stored in the memory cells of the banks are read to sense amplifiers, and immediately written back to the memory cells. A capacitor corresponding to each memory cell is thus recharged to its initial value.
Bit lines interconnect the sense amplifiers with the memory cells. Unfortunately, only a limited number of cells can be attached to each bit line (“BL”). Otherwise, the total load on each BL becomes too great, and the sense amplifiers are no longer able to sense a dumping of a logic “1” or a logic “0” charge from each memory cell.